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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
SUMMARY
The KB2516 is a triple 8-bit analog-to-digital converter optimized for digitizing R/G/B graphics signal from PC and workstation. Its 140MSPS encode rate capability and analog bandwidth of 500MHz supports support display resolution of up to SXGA (1280 x 1024) class. The IC also includes a PLL (Phase Locked Loop) system that can be locked on horizontal line frequency, and generates the ADC clock.
FEATURES
* * * * * * * Analog bandwidth of 500MHz 3 clamps for 256 programmable levels 3 programmable gain amplifiers Analog input range: 0.5Vpp to 1.0Vpp Triple 8-bit ADC Sampling rate up to 140MHz Fully integrated PLL to generate the ADC clock, which can be locked to a HSYNC * * * * * * Integrated PLL divider Programmable clock phase control (step = 7.5) Integrated SOG separator and HSYNC input polarity detector Single and double pixel width output data bus Support I2C and 3-wire serial interface Power down mode 1.25W power dissipation
ORDERING INFORMATION
Device KB2516 Package 144-LQFP-2020 Ordering Information
APPLICATIONS
* * * RGB high speed digitizing LCD desktop monitor Plasma display pannel panel
RELATED PRODUCTS
KS2530 FRC & SCALER
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
BLCOK DIAGRAM
Blue Channel B_OUTA<7:0> Green Channel B_IN G_IN G_IN Red Channel ADC 8-bit Output Drver 8-bit B_OUTB<7:0> G_OUTA<7:0> G_OUTB<7:0> G_OUTA<7:0> R_OUTB<7:0>
CLAMP
CLAMP Gain Control Control
CKA (from PLL)
Output Mode
SDA SCL SEN I2C_3W
Gain Control
PLL HSYNC OUT VSYNC OUT CKA CKA CKB
I2C and 3-wire PLL Control
CLAMP Control
Divider HSYNC IN SOG IN VSYNC IN
Sync Processor
PFD
VCO
2
Phase Shifter
ADC Output Mode Control
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
ELECTRICAL CHARACERISTICS
Symbol Power supply VDDC_P VDDC_A VDDA_A VDDD_A VDD_A VDDR VDD_P VDD_S IDDC_P IDDC_A IDDA_A IDDD_A IDD_A IDDR IDD_P IDD_S Ptot Pre-amp f-3dB VIN Vbs AVmax AcG Af1 Af2 tr tf Vbrt1 Vbrt2 Vbrt3 Amplifier bandwidth RGB input voltage range Input bias voltage Voltage gain max Coarse gain diff. between ch. Fine gain diff. 1 between ch. Fine gain diff. 2 between ch. Pre-amp rising time Pre-amp falling time Brightness voltage (1) Brightness voltage (2) Brightness voltage (3) for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels 0.5 1.7 1.6 -1.0 -1.0 -1.0 500 0.7 1.9 2.3 0.0 0.0 0.0 1 1 1.5 2.3 3.0 1.0 2.1 2.9 1.0 1.0 1.0 MHz Vpp V dB dB dB dB nS nS V V V Pre-amp analog supply voltage for R, G, B channels ADC analog supply voltage ADC analog supply voltage ADC digital supply voltage ADC digital supply voltage Output driver supply voltage PLL supply voltage Interface logic supply voltage Pre-amp analog supply current ADC analog supply current ADC analog supply current ADC digital supply current ADC digital supply current Output driver supply current PLL supply current Interface logic supply current Total power consumption Fclk = 180MHz, ramp input 5V supply 3.3V supply 5V supply 3.3V supply Fclk = 140MHz, ramp input Fclk = 100MHz 1.25 76 for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels for R, G, B channels 4.75 4.75 3.0 4.75 3.0 3.0 3.0 3.0 55 5.0 5.0 3.3 5.0 3.3 3.3 3.3 3.3 65 66 33 10 20 5.25 5.25 3.6 5.25 3.6 3.6 3.6 3.6 75 V V V V V V V V mA mA mA mA mA mA mA mA W Parameter Conditions Min. Typ. Max. Unit
NOTES: 1. Coarse BRT = 80, Fine BRT = 00 2. Coarse BRT = 80, Fine BRT = 80 3. Coarse BRT = 80, Fine BRT = FF
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Symbol Sync processor SOGdet1 SOGdet2 VrefT VrefB INL DNL SNDR MAXrate CT trD tfD fref fclk DRpll fvco tcap trcap step jPLL
Parameter SOG sync detect level 1 SOG sync detect level 2 Reference top voltage Reference bottom voltage DC integral non-linearity DC differential non-linearity Signal to noise & distortion ratio Max. conversion rate Cross talk Digital output rising time Digital output falling time PLL reference clock frequency Maximum clock frequency PLL divider ratio VCO output clock frequency PLL capture time PLL re-capture time Phase shift step PLL jitter
Conditions
Min. 0.1 1.7 1.2
Typ. 1.8 1.3 4 7.5 200
Max. 1.0 1.9 1.4 1.0 0.5 -36 2 2 150 4095 197 300 -
Unit V V V V LSB LSB dB MHz dB nS nS KHz MHz MHz ms us deg ps
Analog-to-digital converter
Fclk = 75MHz, ramp input Fclk = 75MHz, ramp input Fclk = 100MHz
-1.0 -0.5 36 170
Fclk = 100MHz
20 180 512 17
Phase-locked loop
In start-up condition In lock condition Tamb = 25C Fclk = 180MHz
-
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
DIGITAL SPECIFICATIONS
Characteristics Logic input High level input voltage Low level input voltage High level input current Low level input current Input capacitance Logic output High level output voltage Low level output voltage High level input current Low level input current VOH VOL IOH IOL VDD - 0.5 100 100 VSS + 0.5 V V uA uA VIH VIL IIH IIL CIN VDD - 0.5 10 10 5 VSS + 0.5 V V uA UA pF Symbol Min Typ Max Unit
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
PIN ASSIGNMENT
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VSSC_AR VDDC_AR ITEST VDD_DAC VSS_DAC VBB2 VDDD_A VSSD_A VINP VINN VREFT VREFB VDDG VSSG PDB RESETB_EX HSYNCO ADC_CKB ADC_CK VSYNCO VDD_A VSS_A NC2 NC1 VSSR_RA VDDR_RA R_OUTA0 R_OUTA1 R_OUTA2 R_OUTA3 R_OUTA4 R_OUTA5 R_OUTA6 R_OUTA7 VSSR_RB VDDR_RB
VDDA_AR VSSA_AR R_IN VDDC_PR R_VOUT1 VSSC_PR R_CLPC VDDC_AG VSSC_AG VDDA_AG VSSA_AG G_IN VDDC_PG G_VOUT1 VSSC_PG G_CLPC VDDC_AB VSSC_AB VDDA_AB VSSA_AB VSSA_AB VDDC_PB B_VOUT1 VSSC_PB B_CLPC VDDC_SP VSSC_SP CLPex DETCAP SOG_IN HSYNC_IN HSmic SOGOUT VDD_SI VSS_SI I2C_3W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
KB2516 144-TQFP-2020
R_OUTB0 R_OUTB1 R_OUTB2 R_OUTB3 R_OUTB4 R_OUTB5 R_OUTB6 R_OUTB7 VDDR_GA VSSR_GA G_OUTA0 G_OUTA1 G_OUTA2 G_OUTA3 G_OUTA4 G_OUTA5 G_OUTA6 G_OUTA7 G_OUTB0 G_OUTB1 G_OUTB2 G_OUTB3 G_OUTB4 G_OUTB5 G_OUTB6 G_OUTB7 VDDR_GB VSSR_GB B_OUTA0 B_OUTA1 B_OUTA2 B_OUTA3 B_OUTA4 B_OUTA5 B_OUTA6 B_OUTA7
6
ADDR_EX0 ADDR_EX1 SDA SCL SEN COAST ADC_CKEX VDD_PP VSS_PP VDD_PV VCTRL ITEST1 VDD_PC VSS_PC VDD_PO VSS_PO VDD_PD VSS_PD VSS_PK CKB VDD_PK CKC VBB1 VSSR_BB VDDR_BB B_OUTB7 B_OUTB7 B_OUTB6 B_OUTB5 B_OUTB4 B_OUTB3 B_OUTB2 B_OUTB1 B_OUTB0 VSSR_BA VDDR_BA
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
PIN DESCRIPTION
Table 1. Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VSSC_AR VDDC_AR R_IN VDDC_PR R_VOUT1 VSSC_PR R_CLPC VDDA_AG VSSA_AG VSSC_AG VDDC_AG G_IN VDDC_PG G_VOUT1 VSSC_PG G_CLPC VDDA_AB VSSA_AB VSSC_AB VDDC_AB B_IN VDDC_PB B_VOUT1 VSSC_PB B_CLPC VDDC_SP VSSC_SP CLPex DETCAP SOG_IN HSYNC_IN Test Description Red channel ADC 0V analog power supply Red channel ADC 5V analog power supply Red channel analog input signal Red channel pre-amp 5V power supply Red channel pre-amp output signal Red channel pre-amp 0V power supply Red channel clamp control external cap. Green channel ADC 3.3V analog power supply Green channel ADC 0V analog power supply Green channel ADC 0V analog power supply Green channel ADC 5V analog power supply Green channel analog input signal Green channel pre-amp 5V power supply Green channel pre-amp output signal Green channel pre-amp 0V power supply Green channel clamp control external cap. Blue channel ADC 3.3V analog power supply Blue channel ADC 0V analog power supply Blue channel ADC 0V analog power supply Blue channel ADC 5V analog power supply Blue channel analog input signal Blue channel pre-amp 5V power supply Blue channel pre-amp output signal Blue channel pre-amp 0V power supply Blue channel clamp control external cap. SyncProc 5V power supply SyncProc 0V power supply External clamp signal input pin SOG polarity output SOG signal input pin HSYNC signal input pin
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Table 1. Pin Description (Continued) No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Name SOGOUT VDD_SI VSS_SI I2C_3W ADDR_EX0 ADDR_EX1 SDA SCL SEN COAST ADC_CKEX VDD_PP VSS_PP VSS_PV VDD_PV VCTRL ITEST1 VDD_PC VSS_PC VDD_PO VSS_PO VDD_PD VSS_PD VSS_PK CKB VDD_PK CKC VBB1 VSSR_BB VDDR_BB B_OUTB7 B_OUTB6 B_OUTB5 B_OUTB4 B_OUTB3 SOG output signal pin Serial interface 3.3V digital power supply Serial interface 0V digital power supply Serial interface mode selection between I2C and 3-wire Slave address control bit Slave address control bit Serial interface data signal pin Serial interface clock signal pin Signal enable for 3-wire serial interface COAST signal input External analog to digital converter clock input PLL 3.3V phase detector power supply PLL 0V phase detector power supply PLL 0V analog power supply PLL 3.3V analog power supply VCO control voltage Bandgap reference current test pin PLL 3.3V charge-pump power supply PLL 0V charge-pump power supply PLL 3.3V VCO power supply PLL 0V VCO power supply PLL 3.3V digital power supply PLL 0V digital power supply PLL 0V clock driver power supply PLL output clock with ADC frequency (phase control available) PLL 3.3V clock driver power supply PLL output clock with ADC frequency (phase control available) Substrate 0V power supply Blue channel ADC output B driver power supply (0V) Blue channel ADC output B driver power supply (3.3V) Blue channel ADC digital output B bit 7 Blue channel ADC digital output B bit 6 Blue channel ADC digital output B bit 5 Blue channel ADC digital output B bit 4 Blue channel ADC digital output B bit 3 Description
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
Table 1. Pin Description (Continued) No 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Name B_OUTB2 B_OUTB1 B_OUTB0 VSSR_BA VDDR_BA B_OUTA7 B_OUTA6 B_OUTA5 B_OUTA4 B_OUTA3 B_OUTA2 B_OUTA1 B_OUTA0 VSSR_GB VDDR_GB G_OUTB7 G_OUTB6 G_OUTB5 G_OUTB4 G_OUTB3 G_OUTB2 G_OUTB1 G_OUTB0 G_OUTA7 G_OUTA6 G_OUTA5 G_OUTA4 G_OUTA3 G_OUTA2 G_OUTA1 G_OUTA0 VSSR_GA VDDR_GA R_OUTB7 R_OUTB6 Description Blue channel ADC digital output B bit 2 Blue channel ADC digital output B bit 1 Blue channel ADC digital output B bit 0 Blue channel ADC output A driver power supply (0V) Blue channel ADC output A driver power supply (3.3V) Blue channel ADC digital output A bit 7 Blue channel ADC digital output A bit 6 Blue channel ADC digital output A bit 5 Blue channel ADC digital output A bit 4 Blue channel ADC digital output A bit 3 Blue channel ADC digital output A bit 2 Blue channel ADC digital output A bit 1 Blue channel ADC digital output A bit 0 Green channel ADC output B driver power supply (0V) Green channel ADC output B driver power supply (3.3V) Green channel ADC digital output B bit 7 Green channel ADC digital output B bit 6 Green channel ADC digital output B bit 5 Green channel ADC digital output B bit 4 Green channel ADC digital output B bit 3 Green channel ADC digital output B bit 2 Green channel ADC digital output B bit 1 Green channel ADC digital output B bit 0 Green channel ADC digital output A bit 7 Green channel ADC digital output A bit 6 Green channel ADC digital output A bit 5 Green channel ADC digital output A bit 4 Green channel ADC digital output A bit 3 Green channel ADC digital output A bit 2 Green channel ADC digital output A bit 1 Green channel ADC digital output A bit 0 Green channel ADC output A driver power supply (0V) Green channel ADC output A driver power supply (3.3V) Red channel ADC digital output B bit 7 Red channel ADC digital output B bit 6
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Table 1. Pin Description (Continued) No 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Name R_OUTB5 R_OUTB4 R_OUTB3 R_OUTB2 R_OUTB1 R_OUTB0 VDDR_RB VSSR_RB R_OUTA7 R_OUTA6 R_OUTA5 R_OUTA4 R_OUTA3 R_OUTA2 R_OUTA1 R_OUTA0 VDDR_RA VSSR_RA NC1 NC2 VSS_A VDD_A VSYNCO ADC_CK ADC_CKB HSYNCO RESETB_EX PDB VSSG VDDG VREFB VREFT VINN VINP VSSD_A ADC 0V digital power supply ADC 3.3V digital power supply VSYNC output ADC clock output Inverted ADC clock output HSYNC output External inverted reset signal input Power down control pin (input) ADC 0V analog power supply ADC 3.3V analog power supply ADC reference bottom voltage ADC reference top voltage ADC negative input for test ADC positive input for test ADC 0V digital power supply Description Red channel ADC digital output B bit 5 Red channel ADC digital output B bit 4 Red channel ADC digital output B bit 3 Red channel ADC digital output B bit 2 Red channel ADC digital output B bit 1 Red channel ADC digital output B bit 0 Red channel ADC output B driver power supply (3.3V) Red channel ADC output B driver power supply (0V) Red channel ADC digital output A bit 7 Red channel ADC digital output A bit 6 Red channel ADC digital output A bit 5 Red channel ADC digital output A bit 4 Red channel ADC digital output A bit 3 Red channel ADC digital output A bit 2 Red channel ADC digital output A bit 1 Red channel ADC digital output A bit 0 Red channel ADC output A driver power supply (3.3V) Red channel ADC output A driver power supply (0V) No connection
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
Table 1. Pin Description (Continued) No 138 139 140 141 142 143 144 Name VDDD_A VBB2 VSS_DAC VDD_DAC ITEST VDDA_AR VSSA_AR ADC 5V digital power supply Substrate 0V power supply Pre-amp DAC 0V analog power supply Pre-amp DAC 5V analog power supply Pre-amp control DAC current test pin Red channel ADC 3.3V analog power supply Red channel ADC 0V analog power supply Description
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION OF EACH BLOCK AD2516X is equipped with a pre-amp that can control the gain and clamp level and can generate the pixel clock synchronized to input HSYNC through the internal PLL. It then converts the RGB signal from analog -to- digital by synchronizing to the generated clock. It has a maximum conversion speed of 180MHz and is capable of supporting up to UXGA (1600 x 1200).
VOUT1 DAC 8 bit Gain Control
VIN AMP1 AMP2 VOUT (to ADC)
Cex
gm1 gm2
CLAMP Brightness Control
8 bit DAC
Figure 1. Pre-amp Block Diagram
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
Figure 1 is a block diagram of the pre-amp that is used in AD2516X. A clamp circuit is required to set the input DC level because the RGB signal input is AC coupled as it passes through the capacitor to be sent to the preamp. The signal to control the clamp is made from the HSYNC signal in the sync processor block. The clamp level control, which uses an 8-bit DAC, has two modes, first, the coarse level control that controls 3 RGB channels simultaneously and, second, the fine level control that controls each channel clamp level independently. The input signal is gain controlled through the 8-bit DAC for a maximum gain amplification of 2.3dB. As in the clamp level control, the pre-amp has two modes: 1.) coarse level control that controls 3 RGB channels simultaneously and 2.) fine level control which controls them independently.
VIN
T/H
Digital Correction Logic
15 Comps
OVF 4 Channel A<7:0> UDF Output Driver 8
Vref_tap Gen.
8
T/H
31 Comps
5 Output Mode Control
8
Channel B<7:0>
Figure 2. ADC Block Diagram Figure 2 which has the 2-step pipeline configuration is a block diagram of the ADC used in AD2516X. It uses 1 overlap bit for digital correction and supports 3 output modes, signal channel mode, dual channel interleaving mode, and dual channel parallel mode. The sync processor block converts the HSYNC or SOG input to a positive HSYNC signal, which can be processed by PLL, and also makes the clock signal needed for clamp level control from the HSYNC. When HSYNC and SOG inputs enter simultaneously, it is designed to place priority on the HSYNC.
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
HSYNCH DIVCK
CLKADC
HSYNCH PFD VCO Phase Shifter
MUX MUX MUX
0/180 0/180 0/180 CKB CKC
DIVCK
Divider
SYNCHRO 12 bits from Micom HSYNCO, VSYNCO
Figure 3. PLL Block Diagram Figure 3 is a block diagram of the PLL used in AD2516X. It generates the pixel clock by using the positive HSYNC signal from the sync processor block and the divider coefficient determined by the resolution. The reference clock frequency range is between 20kHz - 150kHz and the maximum output clock frequency is 180MHz. It produces two clock signals having the ADC clock frequency and each signal can have 7.5 phase control. AD2516X is controlled entirely through serial interface, which supports two modes -12C bus and 3-wire interface.
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
REGISTER CONFIGRATION
PRE-AMP Sub Addr. 00H 01H 02H 03H 04H 05H 06H 07H 08H Bit <7:0> <7:0> <7:0> <7:0> <7:0> <7:0> <7:0> <7:0> <4> <3> <2> <1:0> 09H <7:0> Name S00<7:0> S01<7:0> S02<7:0> S03<7:0> S04<7:0> S05<7:0> S06<7:0> S07<7:0> PHSYNC HSEL CLPENB CW<1:0> DACTEST<7:0> Description RGB coarse gain control R fine gain control G fine gain control B fine gain control RGB coarse bright control R fine bright control G fine bright control B fine bright control HSYNC (input) polarity HSYNC select Clamp control Clamp pulse width control DAC output selection for test 0 0 0 00 FFH Default Value 80H 80H 80H 80H 80H 80H 80H 80H 00H
ANALOG TO DIGITAL CONVERTER (ADC) Sub Addr. 0AH Bit <7:6> <5> <4> <3> <2:1> <0> Name M<1:0> ADCK_ENB ADCK_INV ADCK_SEL ADOM<1:0> Description Output mode selection ADC clock output enable ADC clock output inverting ADC clock selection control ADC output buffer control Default Value 00 0 0 0 00 0 00H
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
PHASE LOCKED LOOP (PLL) Sub Addr. 0BH Bit <7:6> <5:3> <2:0> 0CH <7> <6> <5:0> 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H <7:6> <5:0> <6> <5:0> <7:0> <7:4> <1:0> <7:0> <7:0> <7:0> <7:4> <3:0> <7:0> <7:0> <7> <6> <5> <4> <3> <2> <1> VSL<11:0> VSL VSD<7:0> CKA_ENB CKB_ENB CKC_ENB CKA_INV CKB_INV CKC_INV VI_GAIN Test <7:0> HSD<11:0> Test <9:0> Name IFRSH<1:0> IFRSEL<2:0> ICPSEL<2:0> VSINV DEINV AC<5:0> BC<5:0> PCOAST CC<5:0> DIV<11:0> Description VCO free running control VCO range control Charge pump current control VSYNC out polarity DEN out polarity CKA phase control CKB phase control COAST (input) polarity CKC phase control Divider control MSB <11:4> Divider control LSB <3:0> Test out length MSB <9:8> Test out length LSB <7:0> Test out delay HSYNC out length MSB <11:4> HSYNC out length LSB <3:0> VSYNC out length MSB <11:8> VSYNC out length LSB <7:0> VSYNC out delay CKA output enable CKB output enable CKC output enable CKA (ADC input clock) inverting CKB inverting CKC inverting PLL VI converter gain control Default Value 00 100 100 0 0 000000 00 000000 0 000000 01101000 0000 00 00000000 00000100 00000000 0100 0000 00000011 00000000 0 0 0 0 0 0 0 03H 00H 00H 00H 04H 00H 40H 68H 00H 00H 00H 00H 24H
HSYNMOD<1:0> HSYNC out polarity
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
I2C AND 3-WIRE SERIAL INTERFACE BLOCK DESCRIPTION Interface Pin: * * Input: In-out: I2C_3W, SEN, SCL, ADDR_EX<1:0> SDA
Pin Description: * * * * * I2C_3W: SEN: SDA: SCL: ADDR_EX<1:0>: Serial interface mode selection 0 I2C interface mode, 1 3-Wire interface mode 3-Wire interface mode data enable signal 0 enable, 1 disable Serial data input output port Serial interface reference clock input I2C slave address identifier
17
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
I2C Timing Diagram
From Master to Slave - S : Start condition - P : Stop condition - rS: Repeated start condition Write Mode: R/W = 0 S Slave Address R/W ACK
From Slave to Master
Sub Address
ACK
Sub Address
ACK
P
Write Mode: R/W = 0 Auto X X A4 A3 A2 A1 A0
Auto: Sub address auto increment control bit - 0: Disable 1: Enable Auto = 0 0XXXXXXX S Slave Address 0 ACK (sub-address) 0XXXXXXX (sub-address) Auto = 1 S Slave Address 0 ACK 1XXXXXXX (sub-address: N) P ACK Data ACK P
ACK
Data
ACK
ACK
Data (sub-address: N)
ACK
Data Data ACK ACK (sub-address: N+1) (sub-address: N+2) Auto = 1 S Slave Address 0 ACK
1XXXXXXX (sub-address: N) P
ACK
Data (sub-address: N)
ACK
Data Data ACK ACK (sub-address: N+1) (sub-address: N+2) Read Mode: R/W = 1 (Auto = X) S Slave Address
R/W ACK Sub Address (N) ACK rS
Data ACK (sub-address: N) P
Data Data Data ACK ACK ACK (sub-address: N+1) (sub-address: N+2) (sub-address: N+3)
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
Wired Interface Timing Diagram
Sub Address Format Auto R/W A4 A3 A2 A1 A0
Write Mode: R/W = 0 Auto: Sub address auto increment control bit - 0: Disable 1: Enable
Auto = 0: SEN SCL SDA Sub-address (N) Data (N) Sub-address (M) Data (M)
Auto = 1: Sub-address auto increment SEN SCL SDA Sub-address (N) Data (N) Data (N+1) Data (N+2)
Figure 4. Wired Interface Write Mode Timing Diagram
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Read Mode: R/W = 1 (auto = X) SEN SCL SDA Sub-address (N) Data (N) Data (N+1) Data (N+2)
From master to slave
From slave to master
Figure 5. Wired Interface Read Mode Timing Diagram
Serial Interface Description Pre-amp Gain Control * * * * Coarse gain control (S00) RGB coarse gain control with same value. (dynamic gain range: 40dB) Fine gain control (S01 - S03) RGB fine gain control independently. (dynamic gain range : 11 dB) Coarse brightness control (S04) RGB coarse brightness control with same value. (clamp range: 0 - 4V) Fine brightness control (S05 - S07) RGB fine bright control independently. (clamp range: -0.5V - 0.5V)
Sync Processor Control * HSYNC selection control (HSEL) HSEL = 0: Internally polarity converted HSYNC is used HSEL = 1: Default HSYNC is used HSYNC input polarity control (PHSYNC) It is available if HSEL = 1 PHSYNC = 0: Default HSYNC input is used PHSYNC = 1: Inverted HSYNC input is used Clamp control clock selection (CLPENB) CLPENB = 0: Internal clamp signal CLPENB = 1: External clamp signal (by CLPex)
*
*
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TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
*
Clamp pulse width control (CW) CW<1:0> 00 01 10 11 Pulse Width 0.31us 0.54us 0.78us 1.01us
*
DACTEST output selection control (DACTEST) Select one of eight DAC output current DACTEST<7:0> 11111111 11111110 11111101 11111011 11110111 11101111 11011111 10111111 01111111 No selection Coarse gain control DAC Red channel fine gain control DAC Green channel fine gain control DAC Blue channel fine gain control DAC Coarse brightness control DAC Red channel fine brightness control DAC select Green channel fine brightness control DAC select Blue channel fine brightness control DAC select Selected DAC
Analog-to-Digital Converter (ADC) Control * Output mode selection (M) M<1:0> 00 01 10 Output mode Single channel output mode Dual channel interleaving output mode Dual channel parallel output mode
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KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
Output mode Single channel output mode
ADC_CK
Channel A Channel B
D0
D1
D2
D3
D4
D5
HZ
Dual channel interleaving output mode
Channel A Channel B D0 D1 D2 D3 D4 D5
Dual channel parallel output mode
Channel A Channel B D0 D1 D2 D3 D4 D5
*
ADC clock output control (ADCK_ENB) ADCK_ENB = 0: Output clock is enabled ADCK_ENB = 1: Output clock is disabled (HZ) ADC clock output inverting control (ADCK_INV) ADCK_INV = 0: Default ADC_CK and ADC_CKB output ADCK_INV = 1: Inverted ADC_CK and ADC_CKB output ADC clock selection control (ADCK_SEL) ADCK_SEL = 0: Internal PLL output is used ADCK_SEL = 1: External clock (ADC_CKEX) is used ADC output buffer state control (ADOM) ADOM<1:0> 00 01 10 11 01010101 10101010 High impedance Output Buffer State Normal output mode
*
*
*
Phase-Locked loop (PLL) Control * VCO free running frequency control (IFRSH) IFRSH<1:0> 00 01 10 11 Free Running Frequency Default VCO max. freq. Increase VCO max. freq. 7.5% Increase VCO max. freq. 15% Increase VCO max. freq. 30%
22
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
*
VCO frequency range control (IFRSEL) IFRSEL<2:0> 000 001 010 011 Frequency Range (MHz) 17 - 53 34 - 78 65 - 103 94 - 118 IFRSEL<2:0> 100 101 110 111 Frequency Range (MHz) 103 - 143 136 - 165 162 - 187 181 - 197
*
Charge pump current control (ICPSEL) ICPSEL<2:0> 000 001 010 011 Current (uA) 50 100 150 350 ICPSEL<2:0> 100 101 110 111 Current (uA) 500 750 1400
*
VSYNCO polarity control (VSINV) VSINV = 0: Non-inverted VSYNC output VSINV = 1: Inverted VSYNC output DENO polarity control (DEINV) DEINV = 0: Non-inverted DENO output DEINV = 1: Inverted DENO output HSYNCO polarity control (HSYNMOD) HSYNMOD<1:0> 00 01 10 11 Output Polarity Positive HSYNCO Negative HSYNCO Same polarity with input HSYNC Inverted polarity with input HSYNC
*
*
*
COAST input polarity control (PCOAST) PCOAST = 0: Default COAST signal is used PCOAST = 1: Inverted COAST signal is used PLL output clock phase control (AC, BC, CC) AC<5:0>: ADC clock phase control BC<5:0>: CKB output clock phase control CC<5:0>: CKC output clock phase control 0 to 47 is available 7.5 phase control by LSB
*
23
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
~ ~
HSYNC ADC_CK ~ ~ HSYNCO td1 tHS_DELAY tHS_LENGTH tHS ~ ~ DENO tDEN_DELAY td3 tHS : HSYNCO period tHS_DELAY : HSYNC input (HSYNC) to HSYNC output (HSYNCO) delay tHS_LENGTH : HSYNC output (HSYNCO) high duration tDEN_DELAY : HSYNCO rising edge to DENO rising edge delay tDEN_LENGTH: Data enable output (DENO) high duration td1 : ADC_CK rising edge to HSYNCO rising edge delay td2 : ADC_CK rising edge to HSYNCO falling edge delay td3 : ADC_CK rising edge to DENO rising edge delay td4 : ADC_CK rising edge to DENO falling edge delay tDEN_LENGTH td4 td2
Figure 6. HSYNCO and DENO Output Timing Diagram * Divider register (DIV) This register controls the PLL frequency. Default value is 1664 (680H) tHS = T x DIV (T: VCO clock period, 512 DIV 4096) HSYNCO duty control (HSD) tHS_LENGTH = HSD x T - td1 + td2, HSD 5 DENO signal delay control (DED) tDEN_DELAY = DED x T - td1 + td3, DED 5 DENO duty control (DEL) tDEN_LENGTH = (DIV - DED - DEL) x T - td3 + td4, DEL 5
* * *
24
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
COAST ~ ~ HSYNCO VSYNCO ~ ~ td5 tVS_DELAY tVS_LENGTH td6
tVS_DELAY tVS_LENGTH td5 td6
: COAST rising edge to VSYNCO rising edge delay : VSYNCO signal length (high duration) : HSYNCO rising edge to VSYNCO rising edge delay : HSYNCO rising edge to VSYNCO falling edge delay
Fig7. VSYNCO Output Timing Diagram * * * VSYNCO signal delay control (VSD) tVS_DELAY = VSD x DIV x T - td5, VSD 0 VSYNCO signal length control (VSL) tVS_LENGTH = VSL x DIV x T - td5 + td6, VSL 1 PLL output clock enable (CKA_ENB, CKB_ENB, CKC_ENB) 0: Output is enabled 1: Output is disabled (low output) PLL output clock inverting control (CKA_INV, CKB_INV, CKC_INV) 0: Non-inverted clock output 1: Inverted clock output PLL VI converter gain control (VI_GAIN) 0: 375 uA/V 1: 470 uA/V
*
*
25
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
TIMING DIAGRAM
CKA (from PLL) 2.1ns AQ AQP QP QOD (single ch.) QOD (dual ch.) 0.23ns 0.5ns
Figure 9. ADC Clock Timing Diagram
26
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
N+1 N+2 N+3 N N+4 N+5 N+6
ADC Main Timing AQ Coarse THA Coarse ADC Track Hold Track Hold Track Hold Track Hold Track Hold Track
Hold
Track
Hold
N-1 Track
N Track
N+1 Track
N+2 Track
N+3 Track
N+4 Track
N+5 Track
Fine THA Fine ADC DCL OUT Output Driver Timing Single Channel Mode QOD DOUTA
Hold
Hold
Hold
Hold
Hold
Hold
Hold
N-1 N-4
N N-3
N+1 N-2
N+2 N-1
N+3 N
N+4 N+1
N-5
N-4
N-3
N-2
N-1
N
N+1
Dual Channel Mode QOD Interleaving Mode DOUTA DOUTB Parallel Mode DOUTA DOUTB N-6
N-5 N-4
N-3 N-2
N-1 N
N+1
N-7 N-6
N-5 N-4
N-3 N-2
N-1 N
Figure 10. ADC Timing Diagram
27
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
APPLICATION CIRCUIT
VCC
0.1uF
0.1uF
75 or 5
75 or 5
75 or 5 0.1uF
0.1uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VSSC_AR VDDC_AR ITEST VDD_DAC VSS_DAC VBB2 VDDD_A VSSD_A VINP VINN VREFT VREFB VDDG VSSG PDB RESETB_EX HSYNCO ADC_CKB ADC_CK VSYNCO VDD_A VSS_A NC NC VSSR_RA VDDR_RA R_OUTA0 R_OUTA1 R_OUTA2 R_OUTA3 R_OUTA4 R_OUTA5 R_OUTA6 R_OUTA7 VSSR_RB VDDR_RB
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
5K
33 33 33 33 33 33 33 33
VDDA_AR VSSA_AR R_IN VDDC_PR R_VOUT1 VSSC_PR R_CLPC VDDC_AG VSSC_AG VDDA_AG VSSA_AG G_IN VDDC_PG G_VOUT1 VSSC_PG G_CLPC VDDC_AB VSSC_AB VDDA_AB VSSA_AB VSSA_AB VDDC_PB B_VOUT1 VSSC_PB B_CLPC VDDC_SP VSSC_SP CLPex DETCAP SOG_IN HSYNC_IN HSmic SOGOUT VDD_SI VSS_SI I2C_3W
KB2516 144-TQFP-2020
R_OUTB0 R_OUTB1 R_OUTB2 R_OUTB3 R_OUTB4 R_OUTB5 R_OUTB6 R_OUTB7 VDDR_GA VSSR_GA G_OUTA0 G_OUTA1 G_OUTA2 G_OUTA3 G_OUTA4 G_OUTA5 G_OUTA6 G_OUTA7 G_OUTB0 G_OUTB1 G_OUTB2 G_OUTB3 G_OUTB4 G_OUTB5 G_OUTB6 G_OUTB7 VDDR_GB VSSR_GB B_OUTA0 B_OUTA1 B_OUTA2 B_OUTA3 B_OUTA4 B_OUTA5 B_OUTA6 B_OUTA7
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33
C2 0.1uF
4.7K
28
VDDA VDDA
C1 R1
33 33 33 33 33 33 33 33
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
ADDR_EX0 ADDR_EX1 SDA SCL SEN COAST ADC_CKEX VDD_PP VSS_PP VDD_PV VCTRL ITEST1 VDD_PC VSS_PC VDD_PO VSS_PO VDD_PD VSS_PD VSS_PK CKB VDD_PK CKC VBB1 VSSR_BB VDDR_BB B_OUTB7 B_OUTB7 B_OUTB6 B_OUTB5 B_OUTB4 B_OUTB3 B_OUTB2 B_OUTB1 B_OUTB0 VSSR_BA VDDR_BA
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
KB2516 (Preliminary)
All supply pins have to be decoupled, with two capacitors: one for high frequencies (approximately 1nF) and one for the low frequencies (approximately 100nF or higher). PLL loop filter (C1, C2, R1)
fn =
1 2
KO I P (C1 + C2 ) N
where :
f n = the natural PLL frequency
K O = the VCO gain
N = the division number
C1 and C2 = capacitors of the PLL filter
fZ =
where :
1 1f and = x n 2 x R1 x C1 2 fZ
f Z = loop filter zero frequency
R1 = the choosen resistance for the filter
= the damping factor
C1, C2, and R1 values are selected to satisfy the following conditions.
f n f ref 0.05
1.5
29
KB2516 (Preliminary)
TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERTER
PACKAGE DIMENSION
22.00 BSC 20.00 BSC 0-7 0.09-0.20
22.00 BSC
20.00 BSC
144-LQFP-2020
0.08 MAX
#144
#1 0.50 BSC
0.17-0.27 0.08 MAX 0.05-0.15 (1.25) 1.40 0.05 1.60 MAX
30
0.60
0.15

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